StochastiCore: A Complete GPU Architecture Based on Stochastic Computing With Yosys-Verified Synthesis, Gate-Level Power, and a Deterministic-Generator Study
Graphics and inference accelerators are built from arrays of binary multipliers and adders whose area and switching cost grow with operand width. Stochastic computing (SC) encodes a value as the probability of a bit being one in a random stream, reducing multiplication to a single AND gate and scaled addition to a multiplexer, and is intrinsically tolerant of bit errors—making it a candidate primitive for area- and reliability-constrained graphics. Prior SC work targets isolated arithmetic blocks, 2-D image filters, or neural-network layers; no prior design integrates SC into a complete graphics-rendering pipeline. We present StochastiCore, a synthesizable GPU pipeline (command processing, SC vertex transform, binary rasterization, SC fragment shading, framebuffer/Z-buffer, and VGA output) implemented in open-source Verilog. We make three contributions beyond integration. First, a theoretical analysis of SC graphics that derives the estimator variance, the binary-to-stochastic quantization bias, the stream-correlation error of multiplication, the white-noise spectrum that makes SC noise act as dithering, and the bit-error-rate at which SC overtakes binary arithmetic—each validated against simulation. Second, a reproducible, gate-level characterization: a single Yosys flow regenerates every cell count (the complete SC compute unit synthesizes to 1,709 primitive cells / 597 iCE40 LUT4, comparable to a single binary MAC-4 at 1,912 / 674 while providing four multiply lanes, a MAC, a , and a lerp), and an activity-driven power model run on the synthesized netlist reports realistic energy including all LFSR, converter, and counter switching. Third, a bitstream-generator study showing that replacing the LFSR bank with a low-cost deterministic low-discrepancy generator reduces generator area 7.5 and generator switching energy 15.4, with a documented accuracy/latency trade-off. Bit-accurate rendering on the verified LFSR model (not an idealized random model) achieves 36.7 dB PSNR at L=1024 and is resolution-invariant; a cycle-accurate frame-time model gives 68 fps at L=256 on 320240. Site-resolved Monte-Carlo fault injection (N=10,000, 95% CI) shows SC compute-domain errors fall below binary above 0.5%$ bit-error rate, while storage and control faults are equally vulnerable and are best protected by conventional means. We report these results honestly: SC is not a per-operation throughput or energy win; its advantages are area parity at higher functional density, a one-gate marginal multiply, graceful degradation, and free anti-banding.